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TeraStatic provides verification services to derive or implement Formal Verification plans for RTL modules and IPs.

 

During the planning phase of a verification project, one of the critical objective of most state-of-the-art verification flows is to identify the portion of functionalities that are either critical (increase confidence on correctness of key functionality) or best covered through properties and assertions rather then simulation-based tests (maximise ROI of Formal Verification effort). To meet this objective a white-box analysis of the Design Under Verification (DUV) is typically very helpful.

TeraStatic’s consultants not only have deep expertise in both black-box and white-box verification approaches, but are also able to analyse RTL or microarchitecture specifications and extract the information needed for an optimal Formal Verification plan that fits in the overall verification effort.

 

During the implementation phase of the Formal Verification plan, TeraStatic consultants, with minimal support from RTL’s designers, will write, debug and prove the required assertions using your favourite language (SVA, PSL, OVL or ITL) and tool.

 

TeraStatic’s Verification Consultants can work at your site or at TeraStatic’s office via a secure connection.