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Objective: extend the life of your legacy RTL module or IP

 

Example Duration: 2 months for an RTL module of 5K RTL lines (1 configuration; VHDL; non-IEEE libraries, comments and blank lines included in count).

 

Description

This solution is designed to address the problem of verifying legacy RTL modules and IPs, even with obsolete specifications, without any support from its RTL designer or architect. A typical scenario could be that of a legacy IP that has undergone several modifications and bug fixes from a number of designers, leading to poor functional quality and maintainability of the RTL.

 

Our consultant will plan and implement a full Formal Verification of the module and deliver the verification infrastructure, a report with all the issues found, and a modified version of the RTL showing structurally clean fixes (no patches).

 

The verified module will be suitable for reuse in other ICs. The verification infrastructure will also enable a safe and fast validation mechanism to support further modifications or implementation of new IP’s features.
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Text Box: Home | Privacy Policy Text Box: SOLUTIONS Text Box: Key Benefits extends IP’s life RTL fixes are part of deliverables extremely low effort required from customer